Personal computers (PC's) and other systems use serial buses such as RS-232. Standardized serial buses such as Peripheral Component Interconnect Express (PCIE) allow for interoperability of a wide variety of peripherals that can be inserted into bus expansion slots in a PC.
Serial buses that use differential data lines can have high data rates, as small voltage differences between the two data lines can be detected by receivers. Noise immunity is increased since noise that is coupled into both data lines does not affect the differential signal.
FIG. 1 shows a differential serial bus. Transmitter 15 receives a stream of data and drives a voltage difference onto wires TX+, TX− in host-transmit pair 18 to represent the data. Receiver 28 compares the voltage on TX+ to the voltage on TX− and generates an output signal to represent the data. The transmitter's output TX+ is the same line or wire as input RX+ for receiver 28, and output TX− is connected to input RX−. A cable containing host-transmit pair 18 may also have power and ground wires and one or more other pairs.
FIG. 2 shows a protocol-layer diagram of a system with a serial bus. Serial bus 20 has two differential pairs. Host-transmit pair 18 contains two data wires (TX+, TX−) that connect from the transmit Tx outputs of host physical layer 16 to the receive Rx inputs of peripheral physical layer 26. The host sends data to the peripheral over serial bus 20 using host-transmit pair 18. Host physical layer 16 generates differential signals on the two data wires of host-transmit pair 18 while peripheral physical layer 26 has a differential receiver. Host data is arranged in packets by host transport layer 12 and a link to the peripheral established by data link layer 14. Physical layers 16, 26 perform framing, indicating the beginning and end of a frame or packet. Data link layers 14, 24 add and check sequence numbers and checksums to ensure that a packet is received properly and without error.
For reply data from the peripheral to the host, host-receive pair 19 is used. Peripheral data is transmitted as differential data by peripheral physical layer 26 and received by a differential receiver in host physical layer 16.
PCIE is a point-to-point bus protocol, so each serial bus can have only two endpoints. Since each serial bus can carry only a limited bandwidth of data, PCIE allows for multiple serial buses to be placed in parallel between a host and a peripheral. Each serial bus between the host and a peripheral is known as a lane. A higher-bandwidth peripheral can be allocated more lanes than a slower peripheral.
FIG. 3 shows a host connecting to a peripheral over 8 lanes. Host 10 has 8 bi-directional serial buses, or lanes available. Lanes 20A-20H connect to peripheral 30, allowing the bandwidth to be increased by a factor of 8 relative to a single serial bus. Lanes 20A-20H can each be a serial bus with two differential pairs that follow the PCIE specification. Peripheral 30 can be a removable card or device plugged into an expansion slot or connector, or could be fixed in place.
FIG. 4 shows a peripheral that uses only half its available lanes. Peripheral 30′ is plugged into slot 1, which has connections for 8 lanes from host 10. However, peripheral 30′ only supports 4 lanes, since it has only 4 serial-bus connections. The first four lanes 20A-20D from host 10 connect to peripheral 30′ in slot 1, but the other 4 lanes 20E-20H from host 10 to slot 1 are not used, since peripheral 30′ only has 4 serial-bus transceivers. During initialization, negotiation occurs between host 10 and peripheral 30′ to determine the maximum number of lanes between the two device endpoints, which is the smaller number of lanes supported by either host 10 or peripheral 30′.
In a traditional parallel bus, signals could connect to other slots and be used by other peripherals. However, the timing requirements of high-speed serial buses such as PCIE require that each bus have only 2 endpoints. Thus each serial bus lane can connect from the host to only one slot. When the peripheral inserted into the slot does not use all serial-bus lanes, then the remaining unused lanes cannot be used by other peripherals in other slots. Thus the four lanes 20E-20H are wasted.
Although serial-bus lanes can have only two endpoints, one of the endpoints could be a bus switch. The bus switch can receive signals from the serial bus lane and re-transmit the signals over a second serial-bus segment. Such bus switches could allow lanes from a host to connect to different slots, based on the needs of the peripherals in those slots.
A software-based bus switch that connects serial buses together may be constructed by using switching software at or above the transport layer (See FIG. 2). The switching software can forward data from one physical layer to another physical layer. However, transport-layer switches can be slow since data must be passed up through the physical, data-link, and transport layers, and then back down from the transport layer to the data-line and physical layers. A physical-layer bus switch may provide for faster data transmission with reduced switch latency.
While such a bus switch is useful, some possible combinations of peripherals can have less than optimal lane allocations. For example, when one peripheral is a 16-lane peripheral, no lanes might remain for another peripheral in slot 2. When the second peripheral is a slow peripheral, it might be desirable to allocate just one lane to this peripheral, with the remaining lanes allocated to the first peripheral. However, the first peripheral may not be able so support an odd number of lanes, since the number of lanes for a peripheral are defined to be 1, 2, 4, 8, 12, 16, or 32. Thus the first peripheral could not support 15 lanes, and would have to drop back to using only 12 lanes, with the remaining 3 lanes being unused.
The parent application disclosed adding an extra serial-bus lane to the host to allow for much more efficient allocations of serial-bus lanes to peripheral slots. The additional host lane gives the host an odd number of lanes, such as 9, 17, 33, 65, etc. A physical-layer bus switch device was also disclosed that can include an extra switch to mux in this extra lane to the peripheral slots. The extra switch can be in a backwards orientation relative to the other bus switches.
FIG. 5 shows a bus switch between a host and peripheral slots for allocating lanes according to the parent application. A physical-layer bus switch may provide for faster data transmission with a reduced switch latency. Host 10 has a total of 16 available. Each of lane 20A-20P has two differential data pairs. Peripheral 30 in slot 1 can have either 8 or 16 lanes, depending on the type of peripheral inserted into the slot. Negotiation and configuration when peripheral 30 is inserted into slot 1, or at system boot-up, can be performed to determine the number of lanes to use.
The first 8 lanes 20A-20H are hardwired to slot 1. These lanes can only connect to peripheral 30. Should peripheral 30 need fewer lanes, such as 4 or 2 or just 1, the remaining 4, 6, or 7 lanes in lanes 20A-20H are unused.
The other 8 lanes 201-20P from host 10 connect to switches 40A-40H, respectively. Each lane connects to just one switch. Each switch connects to two serial-bus segments to two peripheral slots. Thus the 8 lanes 201-20P can connect host 10 to peripheral 30 slot 1, or to peripheral 32 in slot 2.
For example, lane 201 has a segment from host 10 to switch 40A. Switch 40A can connect this lane from host 10 to either a segment to peripheral 30 in slot 1, or to a different serial-bus segment to peripheral 32 in slot 2. This 9th lane from host 10 can be switched by switch 40A to be the 9th lane input to peripheral 30 in slot 1, or switched to be the first lane input to peripheral 32 in slot 2.
Switches 40A-40H can all be switched together, so that peripheral 30 in slot 1 has 16 lanes and peripheral 32 in slot 2 has no lanes, or so that peripheral 30 in slot 1 has 8 lanes and peripheral 32 in slot 2 has 8 lanes.
FIG. 6A is a diagram showing a 16-lane logical link and an extra 1-lane link according to the parent application. Host 50 creates a first logical link to peripheral 30 in slot 1 using its first 8 lanes L1-L8 and its second 8 lanes L9-L16. Peripheral 30 is configured as 16-lane device.
Lane 17 is used to form a second logic link to peripheral 32 in slot 2. Peripheral 32 could be an 8-lane device that is configured as a 1-lane device when the switch controller or configuration software determines that peripheral 32 is a lower-priority device than peripheral 30, which warrants a full 16 lanes. Peripheral 32 could also be a 1, 2, or 4 lane device.
FIG. 6B is a diagram showing switch settings to produce the 16-lane logical link and the extra 1-lane link of FIG. 6A. The first link to peripheral 30 is formed by the direct connection of the first 8 lanes from host 50, and by the second 8 lanes from host 50, L9-L16, which connect to switches 40 (switches 40A-40H of FIG. 5) and then to peripheral 30. Switch controller 59 configures switches 40 to connect the 8 segments from host 50 to peripheral 30.
The second link to peripheral 32 is formed through switch 54. Extra lane 17 from host 50 connects to switch 54, which drives the lane-1 I/O of peripheral 32. Switch controller 59 configures switch 54 to select the serial-bus segment from lane 17 of host 50, rather than the segment to switches 40.
While switching the extra lane is useful, further optimizations of the bus and switch arrangements are desirable. What is desired is lane allocation and switch configurations that are optimized for multiple slots and multiple ports.